Wafer-scale integration of graphene for electro-optic devices

A recent publication in Laser & Photonics Reviews showcases a successful collaboration between IMEC and Graphenea, resulting in the integration of graphene into CMOS processes. This breakthrough enables wafer-scale integration and upscaling of graphene devices and is part of the Graphene Flagship's Work Package 10 (WP10), focused on "Wafer scale integration."

This scientific paper discusses the potential of using graphene in real-world systems and the need to demonstrate its competitive performance, reliability, and a path to large-scale manufacturing. The researchers used single-layer graphene electro-absorption modulators as a test vehicle and integrated them into a 300mm pilot CMOS foundry environment. By analyzing data from hundreds of devices per wafer, they identified and optimized the impact of specific processing steps on the performance. After optimization, they demonstrated a modulation depth of 50 dB/mm and an electro-optical bandwidth of up to 15.1 GHz for 25μm-long devices. These results were achieved using a CMOS-compatible process, which allows for high-volume, low-cost manufacturing. The researchers believe that this work resolves the bottleneck of graphene wafer-scale integration, and the CMOS-compatible processing enables the co-integration of graphene-based devices with other photonics and electronics building blocks on the same chip.

Figure: Wafer-scale graphene manufacturing. Image from Wu et al, Laser & Photonics Reviews 2023.

The researchers conducted processing on a 6-inch graphene layer that was grown using chemical vapor deposition (CVD) and transferred to a semiconductor wafer using Graphenea’s patented transfer process. Wafer-scale devices were built on the graphene layer using damascene contact and hardmask lithography in accordance with industry standards. The researchers found that the quality of the graphene and the electric field homogeneity, which both affect the modulation depth (electro-optic performance) of the final device, are impacted by the surface flatness. To improve flatness, a uniform capping layer was added, resulting in increased device yield. The capping layer also reduced the impact of later integration steps on the graphene layer. Additionally, the time delay involved in constructing damascene contacts affects the contact resistance and the 3dB bandwidth of the electro-absorption modulators (EAMs). By optimizing these three critical processing steps and implementing a dedicated integration approach compatible with CMOS, the researchers achieved a device yield of over 95%, with values for loss, extinction ratio, and 3dB bandwidth comparable to CVD graphene devices previously demonstrated only on much smaller scales and in laboratory conditions.

The findings from this study can be extended to develop a library of sophisticated graphene-based optoelectronic devices, such as modulators, photodetectors, and sensors. The researchers' work will support the industrial adoption of graphene-based photonics devices and pave the way for next-generation datacom and telecommunications applications.