Monolayer Graphene on SiO₂/Si 90 nm
Monolayer Graphene on SiO₂/Si (6" wafer) - Fully Covered - Processed in Clean Room Class 1000
Our monolayer graphene on SiO₂/Si (fully covered) is a bidimensional material produced by CVD and transferred to a circular substrate of SiO₂/Si (90nm) by a wet transfer process. We consider it to be a benchmark product in the graphene market - not only for its excellent quality, but also for its shape, size and number of applications.
- · Growth method: CVD synthesis
- · Appearance (color): Transparent
- · Transparency: > 97%
- · Coverage: > 98%
- · Number of graphene layers: 1
- · Thickness (theoretical): 0.345 nm
- · FET Electron Mobility on Al2O3 passivated SiO2/Si: 6900 cm2 /Vs (doi: http://dx.doi.org/10.1063/1.4972847)
- · FET Electron Mobility on SiO₂/Si: 3760 cm2/Vs DOI: https://doi.org/10.1103/PhysRevLett.119.066802
- · Sheet Resistance on SiO₂/Si: 450±40 Ohms/sq (1cm x1cm)
- · Grain size: Up to 20 μm
- · Dry Oxide Thickness: 90 nm (+/-5%)
- · Type/Dopant: P/B
- · Orientation: <100>
- · Resistivity: 1-10 ohm·cm
- · Thickness: 675 +/- 20 μm
- · Front surface: Single Side Polished
- · Back Surface: Etched
- · Particles: <firstname.lastname@example.org μm
All our samples are subjected to a rigorous QC in order to ensure a high quality and reproducibility of the graphene. All our CVD materials are processed in Clean Room Class 1000. Each batch must pass the following tests:
- · Raman Spectroscopy on each batch: I(G)/I(2D)<0.7; I(D)/I(G)<0.05
- · Optical Microscopy inspection of each individual sample to ensure good transfer quality and purity
If your application requires more specific controls (AFM, SEM...) please do not hesitate to contact us.
Graphene research, Graphene transistors and electronic applications, Graphene optoelectronics, plasmonics and nanophotonics, Graphene photodetectors (measure photon flux or optical power), Biosensors and bioelectronics, Aerospace industry (electronics, thermal interface materials, etc.), MEMS and NEMS
“Recent advances in graphene-based biosensors”, 2011; doi: 10.1016/j.bios.2011.05.039. “Optical nano-imaging of gate-tunable graphene plasmons”, Nature 487, 77-81 (05 July 2012), vol. 487, page 77, doi: 10.1038/nature11254
"Graphene Frequency Multipliers", Electron Device Letters, IEEE, vol. 30, Issue:5; doi: 10.1109/LED.2009.2016443
Frequently Asked Questions
A: It has to be done under dry conditions. When using wafers such as Si or Quartz a diamond pen can be used to cleave it. In order to protect the graphene film from debris, we recommend doing it with the protective PMMA layer on top of graphene. In this case, we can provide you the sample with the PMMA on top.
When using thin substrates such as PET or PEN you can easily cut them using scissors.
A: In principle, additional cleaning is not needed and you can use our graphene directly. However, thermal annealing can be applied on Si or Quartz substrates, typically at 250-400C under inert atmosphere in order to have a cleaner graphene and to reduce absorbents on the graphene surface.
A: Our graphene on SiO2 is p-doped, with a charge carrier density of around 1013 cm-2. This intrinsic doping can be reduced by at least one order of magnitude by thermal treatments, which lower the Dirac voltage down to 40-80 V. Another alternative is using a passivation layer on top of the graphene, which prevents the presence of water between the substrate and the graphene film.
Questions and answers about this Product
Do you have any question? Make it here