GFET-S11 (Die size 10 mm x 10 mm) - Processed in Clean Room Class 1000
The GFET-S11 chip from Graphenea provides 31 graphene devices with a van der Pauw (vdP) geometry, distributed in 3 different sizes. 3 vdPs have a 2x2mm2 footprint, 14 vdPs have a 500x500µm2 footprint and 14 vdPs have a 125x125µm2 footprint. These devices have an optimized geometry for 4-probe measurements in a vdP configuration. These varying graphene device dimensions allow investigation of geometry dependence on device properties, enabling immediate optimization.
- · Growth method: CVD synthesis
- · Chip dimensions: 10 mm x 10 mm
- · Chip thickness: 675 μm
- · Number of GFETs per chip: 31
- · Gate oxide thickness: 90 nm
- · Gate oxide material: SiO2
- · Dielectric Constant of the SiO2 layer: 3.9
- · Resistivity of substrate: 1-10 Ω.cm
- · Metallization: Au contacts
- · Graphene field-effect mobility: >1000 cm2/V.s
- · Dirac point: <50 V
- · Minimum working devices: >75 %
Absolute maximum ratings
- · Maximum gate-source voltage: ± 50 V
- · Maximum temperature rating: 150 °C
- · Maximum drain-source current density 107A.cm-2
All our samples are subjected to a rigorous QC in order to ensure a high quality products.
- · Optical microscopy inspection of all the devices
- · Raman Spectroscopy of each fabrication batch
- · Electrical characterisation of each fabrication batch
Graphene field-effect transistors (GFETs) have unprecedented sensitivity to the surrounding environment and is an ideal transducer for a variety of sensing applications. Depending on the application, GFETs can be tuned to be sensitive only to the stimulus of interest and have shown breakthrough performance in areas such as graphene device research, quantum transport, gas sensors, chemical sensors and magnetic sensors.
"Graphene field effect transistors on flexible substrate: Stable process and high RF performance"
"High-Gain Graphene Transistors with a Thin AlOx Top-Gate Oxide"
Scientific Reports volume 7, Article number 2419 (2017) doi:10.1038/s41598-017-02541-2